The present invention relates to frequency synthesis, in particular for the modulating and demodulating signals, and provides a frequency synthesis method and system using a phase locked loop and having a short phase locking time.
Many methods and systems for synthesizing frequencies to provide an output signal whose frequency is an integer multiple of the frequency of a reference signal are known in the art, in particular methods and systems using a phase locked loop. In these methods and systems, the output signal is compared to a reference signal, normally after frequency division, and the phase difference controls the output.
The output signal is generally generated by a voltage-controlled oscillator (VCO) to which the filtered output signal of the phase comparator is applied, constituting a frequency control input signal.
For example, these methods and systems find applications in the send and receive modules of communication systems, in particular of radiocommunication systems, constituting means for changing send or receive channels.
Frequency synthesizers have been developed more recently that integrate fractional frequency dividers in their phase locked loop and can supply an output signal with virtually any frequency.
On changing channel, it is necessary to modify the frequency of the output signal and therefore to lock the phase locked loop to said new frequency.
These frequency changing and locking procedures lead to non-negligible waiting times and unnecessary consumption of energy and are not user friendly.
To shorten these procedures, it has been proposed in particular to use a fractional division phase locked loop with a variable cut-off frequency band and to precharge an upstream capacitor.
However, this solution is difficult and delicate to implement, necessitates supplemental outputs and an additional implementation surface area, and increases energy consumption.
An object of the present invention is to alleviate the drawbacks previously cited and to propose a solution which can greatly improve the locking time using a fractional phase locked loop without generating unwanted radio frequency interference.
To this end, the present invention provides a frequency synthesis method using a phase locked loop including a phase comparator, said method including a step of switching from a fractional frequency division operating mode to an integer frequency division operating mode after a time or time-delay for stabilizing operation of said loop has elapsed, which method is characterized in that it consists of effecting said operating mode switching by masking or eliminating a portion of the pulses of a reference signal and a comparison signal before they are applied to inputs of the phase comparator.
It also provides a frequency synthesizer system using a phase locked loop and including a generator whose output signal has a frequency controlled as a function of the signal delivered by a phase comparator whose inputs receive a reference signal and a comparison signal coming from a feedback subsystem connecting the output of said controlled frequency generator to an input of said phase comparator and integrating a fractional frequency divider, characterized in that it also includes a generator for generating masking or elimination signals applied, as command or authorization signals, to discriminator or filter circuits connected in series, one in the transmission line for the reference signal and the other in the feedback subsystem immediately upstream of the corresponding inputs of the phase comparator, switching from the fractional frequency division phase locked loop operating mode to the integer frequency division phase locked loop operating mode being effected by applying said masking or elimination signals.
The basic idea of the present invention lies in switching from a fractional division phase locked loop (with no additional implementation) to a conventional phase locked loop (with integer division) after the stabilization time delay, with or without modification of the bandwidth of said phase locked loop and, in any event, without generating interference.
The solution proposed by the invention leads to masking of some pulses, so that the phase comparator is activated as in a conventional phase locked loop after a particular time-delay.